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4-mb (512k x 8) mobl ? static ram cy62148dv3 0 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-05341 rev. *b revised february 10, 2004 features ? very high speed: 55 ns ? wide voltage range: 2.20v ? 3.60v pin-compatible with cy62148cv25, cy62148cv30 and cy62148cv33 ultra low active power ? typical active current: 1.5 ma @ f = 1 mhz ? typical active current: 8 ma @ f = f max (55-ns speed) ultra low standby power easy memory expansion with ce , and oe features automatic power-down when deselected cmos for optimum speed/power packages offered: 36-ball bga, 32-pin tsopii and 32-pin soic functional description [1] the cy62148dv30 is a high-performance cmos static rams organized as 512k words by 8 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption. the device can be put into standby mode reducing power consumption when deselected (ce high). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low and we low). note: 1. for best practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram a 1 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 13 ce a 14 a 15 a 16 a 17 a 18 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12
cy62148dv3 0 document #: 38-05341 rev. *b page 2 of 11 pin configuration [2,3] fbga 32 tsopii 32 soic notes: 2. nc pins are not connected on the die. 3. dnu pins have to be left floating or tied to vss to ensure proper application. a a a 15 v cc a 13 a 12 a 5 nc we a 7 i/o 4 i/o 5 a 4 i/o 6 i/o 7 v ss a 11 a 10 a 1 v ss i/o 0 a 2 a 8 a 6 a 3 a 0 v cc i/o 1 i/o 2 i/o 3 a 17 a 18 a 16 ce oe a 9 a 14 d e b a c f g h dnu we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 v cc a 3 a 2 a 1 a 17 a 16 oe a 6 a 14 ce i/o 2 i/o 0 i/o 1 a 12 a 7 21 22 19 20 i/o 7 27 28 25 26 17 18 23 24 v ss a 5 a 4 i/o 6 i/o 5 i/o 4 i/o 3 a 10 a 18 a 11 a 0 a 9 a 8 a 13 a 15 top view top view top view we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 v cc a 3 a 2 a 1 a 17 a 16 oe a 6 a 14 ce i/o 2 i/o 0 i/o 1 a 12 a 7 21 22 19 20 i/o 7 27 28 25 26 17 18 23 24 v ss a 5 a 4 i/o 6 i/o 5 i/o 4 i/o 3 a 10 a 18 a 11 a 0 a 9 a 8 a 13 a 15
cy62148dv3 0 document #: 38-05341 rev. *b page 3 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .................................. ?65c to +150c ambient temperature with power applied............................................... 55c to +125c supply voltage to ground potential ........................................ ?0.3v to v cc(max) + 0.3v dc voltage applied to outputs in high-z state [4,5] ......................... ?0.3v to v cc(max) + 0.3v dc input voltage [4,5] ......................?0.3v to v cc(max) + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage.......................................... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range product range ambient temperature v cc [6] cy62148dv30l industrial ?40c to +85c 2.2v to 3.6v cy62148dv30ll product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 (ua) f = 1 mhz f = f max min. typ. [7] max. typ. [7] max. typ. [7] max. typ. [7] max. cy62148dv30l 2.2 3.0 3.6 55 1.5 3 8 15 2 12 cy62148dv30ll 2.2 3.0 3.6 55 3 10 8 cy62148dv30l 2.2 3.0 3.6 70 1.5 3 8 15 2 12 cy62148dv30ll 2.2 3.0 3.6 70 3 10 8 electrical characteristics over the operating range parameter description test conditions cy62148dv30-55 cy62148dv30-70 unit min. typ. [7] max. min. typ. [7] max. v oh output high voltage i oh = ?0.1 ma v cc = 2.20v 2.0 2.0 v i oh = ?1.0 ma v cc = 2.70v 2.4 2.4 v v ol output low voltage i ol = 0.1 ma v cc = 2.20v 0.4 0.4 v i ol = 2.1 ma v cc = 2.70v 0.4 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3v 1.8 v cc + 0.3v v v cc = 2.7v to 3.6v 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels l815 815ma ll 10 10 ma f = 1 mhz l 1.5 3 1.5 3 ma ll ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ?0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , and we ), v cc =3.60v l212 212 a ll 8 8 i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v l212 212 a ll 8 8 notes: 4. v il(min.) = ?2.0v for pulse durations less than 20 ns. 5. v ih(max) = v cc +0.75v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c.
cy62148dv3 0 document #: 38-05341 rev. *b page 4 of 11 capacitance for all packages [8] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ.) 10 pf c out output capacitance 10 pf thermal resistance parameter description test condit ions bga tsop ii soic stsop unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 72 75.13 55 105 c/w jc thermal resistance (junction to case) 8.86 8.95 22 13 c/w ac test loads and waveforms parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [7] max. unit v dr v cc for data retention 1.5 v i ccdr data retention current v cc = 1.5v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v l 9 a ll 6 a t cdr [8] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns data retention waveform notes: 8. tested initially and after any design or process changes that may affect these parameters. 9. full device ac operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. 1.5v 1.5v t cdr v dr > 1.5 v data retention mode t r ce v cc
cy62148dv3 0 document #: 38-05341 rev. *b page 5 of 11 switching characteristics (over the operating range) [10] parameter description 55 ns 70 ns unit min. max. min. max. read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [11] 55ns t hzoe oe high to high z [11,12] 20 25 ns t lzce ce low to low z [11] 10 10 ns t hzce ce high to high z [11, 12] 20 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-up 55 70 ns write cycle [13] t wc write cycle time 55 70 ns t sce ce low to write end 40 45 ns t aw address set-up to write end 40 45 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 45 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [11, 12] 20 25 ns t lzwe we high to low z [11] 10 10 ns switching waveforms notes: 10. test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 v/ns), timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 11. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 12. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 13. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 14. device is continuously selected. oe , ce = v il . 15. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha read cycle no. 1 (address transition controlled) [14, 15]
cy62148dv3 0 document #: 38-05341 rev. *b page 6 of 11 notes: 16. address valid prior to or coincident with ce transition low. 17. data i/o is high impedance if oe = v ih . 18. during this period, the i/os are in output state and input signals should not be applied. 19. if ce goes high simultaneously with we high, the output remains in high-impedance state. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current read cycle no. 2 (oe controlled) [15, 16] address t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note write cycle no. 1 (we controlled) [17, 19] 18 t sce
cy62148dv3 0 document #: 38-05341 rev. *b page 7 of 11 switching waveforms (continued) write cycle no. 2 (ce controlled) [17, 19] t wc data in valid t aw t sa t pwe t ha t hd t sd t sce ce address we data i/o oe data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe data in valid write cycle no. 3 (we controlled, oe low) [19] note 18 t pwe t sce truth table ce we oe inputs/outputs mode power h x x high z deselect/power-down standby (i sb ) l h l data out (i/o 0 -i/o 7 ) read active (i cc ) l h h high z output disabled active (icc) l l x data in (i/o 0 -i/o 7 ) write active (icc) ordering information speed (ns) ordering code package name package type operating range 55 cy62148dv30l-55bvi bv36a 36-ball very fine pitch bga (6 mm 8 mm 1 mm) industrial cy62148dv30ll-55bvi 55 cy62148dv30l-55bvxi bv36a 36-ball very fine pitch bga (6 mm 8 mm 1 mm) pb-free industrial cy62148dv30ll-55bvxi 55 cy62148dv30l-55zsxi zs-32 32-pin tsop ii pb-free industrial cy62148dv30ll-55zsxi 55 cy62148dv30l-55sxi s-32 32-pin soic pb-free industrial cy62148dv30ll-55sxi
cy62148dv3 0 document #: 38-05341 rev. *b page 8 of 11 70 cy62148dv30l-70bvi bv36a 36-ball very fine pitch bga (6 mm 8 mm 1 mm) industrial cy62148dv30ll-70bvi 70 CY62148DV30L-70BVXI bv36a 36-ball very fine pitch bga (6 mm 8 mm 1 mm) pb-free industrial cy62148dv30ll-70bvxi 70 cy62148dv30l-70zsxi zs-32 32-pin tsop ii pb-free industrial cy62148dv30ll-70zsxi 70 cy62148dv30l-70sxi s-32 32-pin soic pb-free industrial cy62148dv30ll-70sxi ordering information (continued) speed (ns) ordering code package name package type operating range package diagrams 36-lead fbga (6 x 8 x 1 mm) bv36a 51-85149-*b
cy62148dv3 0 document #: 38-05341 rev. *b page 9 of 11 package diagrams (continued) 51-85095-** 32-lead tsop ii zs32
cy62148dv3 0 document #: 38-05341 rev. *b page 10 of 11 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) 0.546[13.868] 0.440[11.176] 0.101[2.565] 0.050[1.270] 0.014[0.355] 0.118[2.997] 0.004[0.102] 0.047[1.193] 0.006[0.152] 0.023[0.584] 0.793[20.142] 0.450[11.430] 0.566[14.376] 0.111[2.819] 0.817[20.751] bsc. 0.020[0.508] min. max. 0.012[0.304] 0.039[0.990] 0.063[1.600] seating plane 1 16 17 32 0.004[0.102] 32-lead (450 mil) molded soic s34 51-85081-*b
cy62148dv3 0 document #: 38-05341 rev. *b page 11 of 11 document history page document title:cy62148dv30 4-mb (512k x 8) mobl ? static ram document number: 38-05341 rev. ecn no. issue date orig. of change description of change ** 127480 06/17/03 hrt created new data sheet *a 131041 01/23/04 cbd change from advance to preliminary *b 222180 see ecn aju change from preliminary to final added 70 ns speed bin modified footnote #6 and #12 removed max value for v dr on ?data retention characteristics? table modified input and output capacitance values added pb-free ordering information removed 32-pin stsop package

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